With preparatory ISP processing, our SoC solutions achieve an end-to-end latency of less than 10 ms, spanning the full pipeline from image sensor output to display rendering.
We continuously reduce the power consumption of smart devices, significantly enhancing energy efficiency for power-constrained scenarios.
Our SoC supports real-time processing of visible-light signals at a resolution of 4K at 60 fps, enabling high-fidelity visual data handling.
The ISP subsystem integrates four independent on-chip scalers (supporting scaling ratios from 1/64 to 2×), complemented by two external one-inputfour-output scalers, providing flexibility for multi-resolution image adaptation.
The CV ISP module integrated in our SoC solutions supports two-channel mono sensor input and operates independently without consuming resources allocated to the RGB ISP.
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